High pass filters pass high frequency signals above a cutoff frequency and attenuate low frequency signals below the cutoff frequency. High pass filters typically cannot achieve very low cutoff frequencies due to diode leakage current.
Referring now to FIG. 1, a high-pass filter 10 with amplifiers Amp1, Amp2 is shown. A capacitor CHP is connected to an output of Amp1, and an input of Amp2. Resistors R1, R2, . . . , and Rn are connected in parallel to one end of the capacitor CHP and the input of Amp2, and to a source node of transistors M1, M2, . . . , and Mn and a cathode of diodes D11, D21, . . . , and Dn1. A source node of transistor MCH is connected to one end of the capacitor CHP and the input of Amp2, and to a cathode of diode Do1. A drain node of transistors M1, M2, . . . , Mn, and MCH is connected to a cathode of diodes D12, D22, . . . , Dn2, and Do2 and to the reference node VREF. The anodes of diodes D11, D21, . . . , Dn1, D12, D22, . . . , Dn2, Do1, and Do2 are connected to ground.
The transistors M1, M2, . . . , Mn, and MCH receive control signals MSW1, MSW2, . . . , MSWn, and CLK, respectively, which control transistors M1, M2, . . . , Mn, and MCH. Transistors M1, M2, . . . , and Mn open or close bias networks 20 of different resistances based on a desired cutoff frequency of the high-pass filter. A time constant, τ=RCHP, is inversely proportional to a cutoff frequency. The cutoff frequency represents the frequency at which the output power is half the input power. The transistor MCH is controlled by the clock signal CLK and is used to charge the capacitor CHP using voltage VREF during initialization. For example, the resistance through paths R1, R2, . . . , and Rn may be too large, thereby increasing a time to charge capacitor CHP.
Referring now to FIG. 2, a bias network 20 of the high pass filter 10 is shown in more detail. For example, the bias network 20 includes an NMOS transistor M1 fabricated using a twin-well process. A resistor R1 is connected at one end to a communication node VC, and at the other end to a source of the transistor M1 and a cathode of a diode D11. The drain of transistor M1 is connected to a cathode of diode D12 and a reference node VREF1. Control signal MSW1 controls the switching of transistor M1. Anodes of diodes D11, D12 are connected to an anode of diode D13. A cathode of diode D13 is connected to a second reference node VREF2 and to a cathode of diode D14. An anode of diode D14 is connected to ground.
Referring now to FIG. 3, a cross-sectional view of an NMOS transistor 30 created using a twin-well process is shown. A deep n-well 34 is formed in a p-type substrate 32. A p-well 36 is formed in the deep n-well 34. An n+ source region 38 and an n+ drain region 40 are formed in the p-well 36. Diodes D11-D14 are inherent in regions between n-type and p-type regions (i.e. p-n junctions). For example, current flows from the p-type side (the anode) to the n-type side (the cathode). In other words, a diode D11 is inherently present in the region 42 between the source 38 and the p-well 36. Similarly, a diode D12 is inherently present in the region 44 between the drain 40 and the p-well 36. A diode D13 is inherently present in the region 46 between the p-well 36 and the deep n-well 34. A diode D14 is inherently present in the region 48 between the deep n-well 34 and the p-type substrate 32.